1. Field of the Invention
The present invention concerns an electronic circuit which is an automatically stabilized, latched differential comparator with pre-amplification and with a single clock. This comparator is designed to work at very high speeds (with microwaves of up to several gigahertz): its single clock, its automatically stabilized rest voltages and its architecture are such that it is affected very little by technological variations in the manufacture of transistors which cause measuring errors or instability.
This comparator has been designed to be made in integrated circuit form using III-V group materials such GaAs but, of course, it can also be made of silicon without going beyond the scope of the invention: only its working speed is lower.
2. Description of the Prior Art
Differential latched comparators use the mechanism of positive feedback the difference in voltages between inputs is found again, after amplification, at the outputs (measurement phase). It is then that these signals are re-injected into the inputs (divergence phase). The fact of looping the outputs back to the inputs leads to a fast amplification of the voltage differences
A structure of this type, provided with a balance-resetting circuit, becomes very valuable since it enables the making of comparators with a very small flip-over time.
FIG. 1 gives an example of an electrical diagram of a latched comparator with imbricated differential stages, according the prior art.
The input signals, E.sub.1 and E.sub.2, addressed to the gates of the transistors T.sub.6 and T.sub.7, are coupled with the output signals S.sub.1 and S.sub.2, taken at the gates of the transistors T.sub.8 and T.sub.9, namely also at the drains of the transistors T.sub.6 and T.sub.7. In this architecture, it is necessary to have two complementary clocks, H.sub.1 and T.sub.2, the pulses of which are applied to the gates of the transistors T2 and T3.
This comparator has two imbricated differential stages: an internal stage T.sub.2 +T.sub.4 +T.sub.5 +T.sub.8 +T.sub.9 and an external stage T.sub.3 +T.sub.6 +T.sub.7 +T.sub.8 +T.sub.9. In this structure, the passage from the measuring phase to the divergence phase is achieved by switching over the current of the external differential stage to the internal differential stage by means of clocks and transistors, T.sub.2 +T.sub.3, whereupon the divergence starts.
The voltage level translators (T10, D1, D2, D3, T12) and (T11, D4, D5, D6, T13) are indispensable to compensate for the difference in resting levels existing between the inputs and the outputs.
The drawbacks related to this structure are chiefly:
the need for complementary clocks H.sub.1 and H.sub.2 without overlapping, PA1 the lack of sensitivity, due to the injection of charges during switching-over operations, PA1 the absence of stabilization of resting levels to cope with technological imperfections, because it is not always verified that: EQU I.sub.T1 =I.sub.T4 +I.sub.T5 PA1 the instability of the output signals due to switching-over of current when going from the external stage to the internal stage and vice versa. PA1 compensation for technological variations, due to the stabilization of voltages, PA1 operation with a single clock, PA1 high sensitivity of elimination of the transfer of current between the internal circuit and the external circuit.
A comparator according to the invention makes it possible to overcome these drawbacks through:
The invention uses circuit elements known per se, such as a differential amplifer at input, a divergence circuit and voltage level translators at output, but the coupling between the differential amplifier and the divergence circuit is achieved by means of two voltage followers which isolate the amplifer from the divergence circuit. The rest voltage at the outputs of the amplifier may then be imposed by a automatic control loop. The coupling between the differential amplifier and the divergence circuit is achieved on the gate of the load transistors of this circuit, said transistors being themselves mounted in series, each with an insulation transistor which can work either in resistive mode or in saturated mode.